1. Field of the Invention
The present invention generally relates to hardware description language (HDL), and more particularly to HDL simulations with negative setup and/or hold times.
2. Description of the Related Art
Hardware description language (HDL) may be used in designing all types of electronic circuits. These electronic circuits may include application specific integrated circuits (ASICs) and/or very large scale integration (VLSI) circuits. HDL may allow each described Hard Macro Core (HMC) to have connections to other HMCs and/or the function of the interacting HMCs may be simulated. Simulation for approximating the function of an electronic circuit may be used before the electronic circuit goes into production.
In a conventional HDL method, a HMC may be integrated with other circuit elements and then simulated. A timing model of the HMC may be produced as one step in the simulation process. The timing model may have timing information that relates at least one pin connected to the HMC. The timing information may include parameters, for example a setup time and/or a hold time, with respect to each pin.
HDL simulation may not permit a negative number to represent a negative parameter, such as the setup time and/or hold time. Therefore, in conventional methods, a value of zero instead of a negative value may be used to represent setup time and/or hold time. However, this may provide a less accurate simulation as a negative setup time and/or hold time may exist relative to a signal.